VERILOG2097: State-dependent path conditions in specify blocks should stick with the subset of expression types and operators defined by SystemVerilog standard

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

LOW	-	-	Consistency \| Conventional	10min	synthesis, portability, vscode, simulation, linter

Description

Noncompliant code example

module fly(input b, output c);
  wire integer a;
  specify
    if (a === 1 + 1) (b => c) = (0,0); // Noncompliant: 'a === 1 + 1' expression is not valid in a state-dependent path condition
  endspecify
endmodule

State-dependent path conditions in specify blocks are restricted to a subset of expression types and operators (see SystemVerilog standard, Table 30-1 for the list of valid operators).

Even if some tools allow more expression types and operators, stick to the standard to keep your code portable.

Parameters

No parameters.