VERILOG2119: Implicit named port connection should not be made between two inequivalent types

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

MEDIUM	-	-	Intentionality \| Logical	5min	synthesis, portability, vscode, linter, simulation

Description

An implicit named port connection is made between two inequivalent types. Unlike with a normal port connection, where the type of the connection undergoes implicit conversion, the SystemVerilog standard specifies that this case is an error.

Even if some tools support this syntax, you should refrain from using it to keep your code portable.

Noncompliant code example

module fly(logic p);
endmodule

module dream;
  int p;
  fly fly1(.p);
endmodule

Parameters

No parameters.