VERILOG2126: All conditions should be different within the same “if / else if” conditional statement

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

HIGH	-	-	Intentionality \| Logical	20min	synthesis, vscode, linter, simulation

Description

Having two identical conditions within an if / else if conditional statement is likely a bug (coming, for instance, from a copy/paste).

Noncompliant code example

if (s1 == 0 && s2 == 1) // Noncompliant: The last condition is the same
  q <= 1;
else if (s1 == 0 && s2 == 0)
  q <= 0;
else if (s1 == 0 && s2 == 1)
  q <= 0;

Compliant solution

if (s1 == 1 && s2 == 1)
  q <= 1;
else if (s1 == 0 && s2 == 0)
  q <= 0;
else if (s1 == 0 && s2 == 1)
  q <= 0;

Parameters

No parameters.