VHDL009: Entity names should be unique in a project

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

-	-	LOW	Intentionality \| Clear	30min	synthesis, do254, linter, do254-dr3, simulation, naming

File 1:
entity fly is
  ...
end;

File 2:
entity fly is
  ...
end;

File 1:
entity fly is
  ...
end;

File 2:
entity dream is
  ...
end;

Two entities with the same name cannot be synthesized/simulated for a same FPGA target project.

No parameters.