VHDL025: Only allowed port modes should be used: ‘in’, ‘out’ and, for top-level entities only, ‘inout’

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

HIGH	-	-	Intentionality \| Logical	20min	synthesis, vscode, linter, simulation, cnes, cnes-std-03300

Description

Buffer authorizes an output of an entity to be read inside the entity. Manufacturers of synthesis software do not recommend buffer mode usage because buffers may give some problems during synthesis.

Thus, the usage of port should be restricted to the following modes: in, out and, for top level entities only, inout.

Set sonar.hdl.topModule property at project level for your analysis to be accurate.

Noncompliant code example

With sonar.hdl.topModule set to my_top_level_entity

entity my_entity is
  port(
    a : in std_logic; -- Compliant
    b : out std_logic; -- Compliant
    c : buffer std_logic; -- Noncompliant: 'buffer' is not allowed
    d : inout std_logic -- Noncompliant: 'inout' is not allowed as 'my_entity' entity is not defined as top level entity
  );
end;

Compliant solution

With sonar.hdl.topModule set to my_top_level_entity

entity my_top_level_entity is
  port(
    a : in std_logic; -- Compliant
    b : out std_logic; -- Compliant
    d : inout std_logic  -- Compliant: 'inout' is allowed as 'my_top_level_entity' entity is defined as top level entity
  );
end;

Parameters

No parameters.