VHDL028: Forbidden operators should not be used

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

MEDIUM	-	-	Intentionality \| Logical	5min	synthesis, vscode, linter

Description

Operators **, /, mod, rem, abs, sll, srl, sla, sra, rol, and ror are not synthesizable or only synthesizable with important restrictions.

This rule raises an issue:

On any usage of abs, sll, srl, sla, sra, rol, or ror
On usage of /, mod or rem, whose right operand is not a hardcoded value/constant/generic and not a power of 2
On usage of ** whose left operand is not 2

Note that this rule does not apply to generic and constant declarations.

Noncompliant code example

a <= 8 mod 3; -- Noncompliant: '3' is not a power of 2
b <= 8 mod my_signal; -- Noncompliant: 'my_signal' is not a constant but a signal

Compliant solution

i <= 8 mod 2;
i <= 8 mod my_constant;

Parameters

No parameters.