VHDL032: Signals should not be initialized in their declaration

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

LOW	-	-	Intentionality \| Logical	5min	synthesis, vscode, linter, cnes, cnes-std-06800

architecture my_architecture of my_entity is
  signal my_signal_1 : std_logic := '0'; -- NonCompliant
begin
end;

With default allowSignalInitializationThroughFunction parameter value: false

architecture my_architecture of my_entity is
  signal my_signal : std_logic;
begin
  my_signal := '0';
end;

With allowSignalInitializationThroughFunction parameter value set to true

architecture my_architecture of my_entity is
  signal my_signal : std_logic_vector(7 to 0) := init(kbits);
begin
end;

Setting default value to signal in declaration section is usually not synthesizable and, thus, should be avoided in synthesis files.

Parameter	Value	Description

allowSignalInitializationThroughFunction	false	Set to 'true' to allow signal initialization through function, set to 'false' otherwise.