VHDL1033: Reset signals not used as reset of a flip-flop should be reviewed

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

HIGH	-	-	Intentionality \| Logical	20min	synthesis, bug-finder, do254, reset, do254-ss9, linty-ultra

Description

Noncompliant code example

process(clk, rst) is
begin
  if rst = '1' then
    rst <= '0'; -- Noncompliant: 'rst' reset signal is reused in a non-reset way
  elsif rising_edge(clk) then
    s <= '0';
  end if;
end process;

Compliant solution

process(clk, rst) is
begin
  if rst = '1' then
    s <= '1';
  elsif rising_edge(clk) then
    s <= '0';
  end if;
end process;

All reset signals not used as (synchronous or asynchronous) reset of a flip-flop should be carefully reviewed.

Parameters

No parameters.