VHDL1069: Signals and variables should be assigned a value before being used

Summary

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Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags
HIGH	-	-	Intentionality | Logical	30min	synthesis, bug-finder, do254, do254-cp10, linty-ultra

Description

All signals and variables should be assigned a value before being used.

Noncompliant code example

entity top is
  port(
    i1 : in std_logic;
    i2 : in std_logic;
    o1 : out std_logic;
    o2 : out std_logic
  );
end;

architecture rtl of top is
  signal s : std_logic;
begin
  process(s, i1, i2) is
  begin
    if (s = '0') then -- Noncompliant: 's' has not been initialized
      o1 <= '1';
    else
      o1 <= '0';
    end if;
  end process;

  process(i1, i2) is
    variable v : std_logic;
  begin
    if (v = '0') then -- Noncompliant: 'v' has not been initialized
      o2 <= '1';
    else
      o2 <= '0';
    end if;
  end process;
end;

Compliant solution

entity top is
  port(
    i1 : in std_logic;
    i2 : in std_logic;
    o1 : out std_logic;
    o2 : out std_logic
  );
end;

architecture rtl of top is
  signal s : std_logic;
begin
  process(s, i1, i2) is
  begin
    s <= i1 or i2;
    if (s = '0') then -- Compliant: 's' has been initialized
      o1 <= '1';
    else
      o1 <= '0';
    end if;
  end process;

  process(i1, i2) is
    variable v : std_logic;
  begin
    v := i1 or i2;
    if (v = '0') then -- Compliant: 'v' has been initialized
      o2 <= '1';
    else
      o2 <= '0';
    end if;
  end process;
end;

Parameters

No parameters.