VHDL1070: Clock names should not contain frequency information

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

-	-	LOW	Intentionality \| Clear	10min	cnes-custom, synthesis, bug-finder, cnes-custom-cne-00200, linty-ultra

Description

Noncompliant code example

entity top is
  port(
    clk10MHz : in std_logic;
    ...
  );
end;

Compliant solution

entity top is
  port(
    clk_fly : in std_logic;
    ...
  );
end;

To improve portability and changeability, clock signal names should not contain any frequency information. An issue is raised when a clock signal name contains some digits.

Parameters

No parameters.