VHDL1071: Signals should not be initialized from other signals

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

HIGH	-	-	Intentionality \| Logical	20min	synthesis, bug-finder, linty-ultra

Description

Noncompliant code example

entity fly is
  port(
    i1 : in std_logic;
    ...
  )
end;

architecture dream of fly is
  signal sleep : std_logic := i1; // Noncompliant
begin
  ...
end case;

Signal initialization depending on other signals are ignored.

Parameters

No parameters.