VHDL128: Ports should be given a mode when declared

Summary

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Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags
-	-	LOW	Intentionality | Clear	2min	synthesis, vscode, simulation, linter

Description

Noncompliant code example

port (
  no, test : in std_logic;
  clk_in : in std_logic;
  clk_out : out std_logic;
  clk_div : std_logic -- Noncompliant
);

Compliant solution

port (
  no, test : in std_logic;
  clk_in : in std_logic;
  clk_out : out std_logic;
  clk_div : out std_logic
);

All declared ports should be given a mode.

Parameters

No parameters.