VHDL139: Signals and variables should not be assigned in multiple processes or equivalent concurrent assignments

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

MEDIUM	-	-	Intentionality \| Logical	20min	synthesis, do254, vscode, do254-ss6, linter, simulation, beta

architecture a of e is
begin
  f <= not ((a and b) or c);
  with a select f <= '0' when '0', '1' when others;
end;

architecture a of e is
begin
  f <= not ((a and b) or c);
  with a select g <= '0' when '0', '1' when others;
end;

Signals and variables should not be assigned in multiple processes or equivalent concurrent assignments.

No parameters.