VHDL156: The ports defined in a component should be the same as the ones defined in its corresponding entity

Summary

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Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags
-	-	MEDIUM	Intentionality | Clear	5min	synthesis, linter, simulation

Description

The ports defined in a component should be the same as the ones defined in the corresponding entity.

Related rules

• Direct instantiation should be applied whenever possible

Noncompliant code example

entity inv is
  port(
    a : in std_logic;
    f : out std_logic
  );
end;

entity mux2i is
  port(
    a, b : in std_logic;
    f : out std_logic
  );
end;

architecture a of mux2i is
  component inv is
    port(
      a : in std_logic;
      g : out std_logic -- Noncompliant: 'g' port does not correspond to the 'inv' entity ports names
    );
  end component;
begin
end;

Compliant solution

entity inv is
  port(
    a : in std_logic;
    f : out std_logic
  );
end;

entity mux2i is
  port(
    a, b : in std_logic;
    f : out std_logic
  );
end;

architecture a of mux2i is
  component inv is
    port(
      a : in std_logic;
      f : out std_logic
    );
  end component;
begin
end;

Parameters

No parameters.