VHDL166: Recursive functions should not be used

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

MEDIUM	-	MEDIUM	Intentionality \| Logical	2min	synthesis, do254, vscode, simulation, linter, do254-cp9

Description

Articles & blog posts

Recursive functions in VHDL

Recursive functions should most of the time avoided because they are usually hard to understand.

But note that, sometimes, recursive function are easier to understand as their non-recursive counterpart (such as the below example). In this case, just flag the issue as Won't fix with a proper comment.

function exor( num : std_logic_vector ) return std_logic_vector is
  variable numf : std_logic_vector(num'length-1 downto 0) := (others => '0');
  variable exorf : std_logic_vector((num'length/2)-1 downto 0) := (others => '0');
begin
  numf := num;
  if(num'length = 4) then
    exorf := numf(1 downto 0) xor numf(3 downto 2);
  else
    exorf := exor(numf(num'length-1 downto num'length/2)) xor exor(numf((num'length/2)-1 downto 0));
  end if;
  return exorf;
end;

Parameters

No parameters.