VHDL182: Avoid using arrays with too many dimensions

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

MEDIUM	-	MEDIUM	Intentionality \| Clear	30min	cnes-custom, synthesis, vscode, cnes-custom-cne-05500, linter

Description

Noncompliant code example

With default maximum allowed number of dimensions: 2

type data_vector_1 is array (0 to 7) of integer range 0 to 7;
type data_vector_ is array (0 to 7, 0 to 7, 0 to 7) of integer range 0 to 7; -- Noncompliant: 3 dimensions

type array_type1 is array(0 to 7) of bit;
type array_type2 is array(0 to 7, 0 to 7) of array_type1; -- Noncompliant: 3 dimensions

Compliant solution

With default maximum allowed number of dimensions: 2

type data_vector_1 is array (0 to 7) of integer range 0 to 7;
type data_vector_2 is array (0 to 7, 0 to 7) of integer range 0 to 7;

type array_type1 is array(0 to 7) of bit;
type array_type2 is array(0 to 7) of array_type1;

Avoid using arrays with too many dimensions that are hard to understand.

Note also that some synthesis tools do not support multi-dimensional arrays. If you are using such a synthesis tool, you should set the maxDimensions parameter to 1.

Parameters

Parameter	Value	Description

maxDimensions	2	Maximum allowed number of dimensions