VHDL186: An entity declaration should only contain ports, generics and attributes

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

-	-	LOW	Adaptability \| Focused	30min	synthesis, vscode, simulation, linter

Description

For better portability, an entity declaration should only contain:

ports
generics
attribute declarations
attribute specifications

Noncompliant code example

entity e is
 generic(
    g1 : natural range 0 to 63 := 32;
    g2 : natural range 0 to 31 := 8
  );

  port(
    s1 : in std_logic;
    s2 : out std_logic
  );

  attribute p_type: ic_package;
  attribute p_type of c : component is p1;

  package p is  -- Noncompliant: Package declaration is not allowed
  end;
end;

Compliant solution

entity e is
 generic(
    g1 : natural range 0 to 63 := 32;
    g2 : natural range 0 to 31 := 8
  );

  port(
    s1 : in std_logic;
    s2 : out std_logic
  );

  attribute p_type: ic_package;
  attribute p_type of c : component is p1;
end;

Parameters

No parameters.