VHDL188: Instantiations should be done by name, not by position

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

MEDIUM	-	MEDIUM	Intentionality \| Clear	10min	synthesis, readability, vscode, linter, simulation, cnes, cnes-std-01400

Description

Instantiation by name improves readability as there is no need to look to the entity definition to know the connection between port and signal. It reduces risks of inconsistency between the entity definition and the component instantiation in case of entity modification.

Noncompliant code example

mux1 : Mux
  port map (i_Mux_Input1, i_Mux_Input2, i_Sel, o_Mux_Output);

Compliant solution

mux1 : Mux
  port map (
    i_A => i_Mux_Input1,
    i_B => i_Mux_Input2,
    i_S => i_Sel,
    o_O => o_Mux_Output
  );

Parameters

No parameters.