VHDL190: Variables should only be used in processes, functions and procedures

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

MEDIUM	-	-	Intentionality \| Logical	20min	synthesis, vscode, cnes-std-06300, linter, cnes

Description

VHDL signal is the object used to describe an electrical wire connection or a register. VHDL signal is the way to have a communication between VHDL processes, whereas variable were meant to store a value inside a VHDL process. A variable is assigned without any delay whereas signal assignment lead to an event after a delta delay. This difference can induce design errors or simulation and synthesis mismatch. Thus, variable should only be used in processes, functions and procedures.

Related rules

Variables should not be used

Noncompliant code example

entity e is -- Noncompliant: Variable v not declared in process or function or procedure
  variable v : std_logic;
begin
  ...
end;

Compliant solution

process -- Compliant: Variable v declared in process
  variable v : std_logic;
begin
  ...
end process;

Parameters

No parameters.