VHDL193: Direct instantiation should be applied whenever possible

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

-	-	LOW	Consistency \| Conventional	10min	synthesis, readability, vscode, linter, simulation

Description

Noncompliant code example

architecture a of e is
  component does_something -- Noncompliant: Component declaration followed by component instantiation below
  port (
    a : in std_logic;
    b : out std_logic
  );
  end component does_something;

begin
  DOES_SOMETHING : does_something -- Component instantiation
    port map (
      a => a,
      b => b
    );
end architecture;

Compliant solution

architecture a of e is
begin
  DOES_SOMETHING : entity does_something(rtl) -- Compliant: Direct instantiation
    port map (
      a => a,
      b => b
    );
end architecture;

For better readability, direct instantiation (also called entity instantiation) should be used whenever possible.

This rule raises an issue for each component declaration in package or architecture declarative part.

Articles & blog posts

Entity instantiation and component instantiation

Parameters

No parameters.