VHDL238: All conditions should be different within the same “if / elsif” conditional statement

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

HIGH	-	-	Intentionality \| Logical	20min	synthesis, vscode, linter, simulation

Description

Noncompliant code example

if (s1 = '0' and s2 = '1') then -- Noncompliant: The last condition is the same
  q <= 1;
elsif (s1 = 0 and s2 = '0') then
  q <= 0;
elsif (s1 = '0' and s2 = '1') then
  q <= 0;
end if;

Compliant Solution

if (s1 = '1' and s2 = '1') then
  q <= 1;
elsif (s1 = 0 and s2 = '0') then
  q <= 0;
elsif (s1 = '0' and s2 = '1') then
  q <= 0;
end if;

Having two identical conditions within an if / elsif conditional statement is likely a bug (coming, for instance, from a copy/paste).

Parameters

No parameters.