VHDL240: “case” statement should not have too many cases

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

MEDIUM	-	MEDIUM	Intentionality \| Efficient	30min	synthesis, vscode, simulation, linter

Description

case statement with too many cases may produce design with poor performance and/or hard to understand. Design should be rethought to split large case statements.

Noncompliant code example

With maxNumberOfCases parameter set to 4:

architecture a of e is
begin
  process (data_in)
  begin
    case data_in is
      when s1 | s2 | s3 | s4 =>
        data_out <= "000";
      when s5 => -- Noncompliant: 5 cases (s1, s2, s3, s4 and s5)
        data_out <= "010";
    end case;
  end process;
end architecture;

Compliant solution

With maxNumberOfCases parameter set to 4:

architecture a of e is
begin
  process (data_in)
  begin
    case data_in is
      when s1 | s2 | s3 =>
        data_out <= "000";
      when s4 =>
        data_out <= "010";
    end case;
  end process;
end architecture;

Related rules

"case" statement should not have too many "when" clauses

Parameters

Parameter	Value	Description

maxNumberOfCases	16	Maximum allowed number of cases.