VHDL316: An entity should not have too many ports

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

-	-	MEDIUM	Adaptability \| Focused	20min	synthesis, vscode, linter

Description

Articles & blog posts

Effective Coding with VHDL (4.1 Modularity), Ricardo Jasinski

Noncompliant code example

With default maximum number of ports: 6

entity too_many_responsibilities is
  port (
    clk1 : in std_logic;
    clk2 : in std_logic;
    rst1 : in std_logic;
    rst2 : in std_logic;
    i1 : in std_logic;
    i2 : in std_logic;
    o1 : out std_logic;
    o2 : out std_logic
  );
end entity;

Compliant solution

With default maximum number of ports: 6

entity single_responsibility is
  port (
    clk : in std_logic;
    rst : in std_logic;
    data_in : in std_logic;
    dat_out : out std_logic
  );
end entity;

An entity should have a single and well-defined responsibility. Such an entity is easier to understand, change, maintain, test and reuse. Too many ports is an indication that the entity has too many responsibilities.

Parameters

Parameter	Value	Description

max	6	The maximum allowed number of ports.
checkTopEntity	false	Set to 'true', to check this rule on top entity, set to 'false' otherwise.