VHDL319: Reserved words in future VHDL standards should not be used as identifiers

Summary

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Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags
-	-	HIGH	Consistency | Conventional	10min	synthesis, portability, vscode, linter, simulation

Description

Noncompliant code example

entity view is -- Noncompliant: 'view' is a reserved word in VHDL 2019
...
end;

Compliant solution

entity fly is
...
end;

Make sure to not use reserved words in future VHDL standards as identifiers. If you do not use any reserved words, your code will be compatible with future VHDL standards without having to make any changes.

1076-2019 - IEEE Standard VHDL Language Reference Manual, 15.10 Reserved words

abs	fairness	nand	select
access	file	new	sequence
after	for	next	severity
alias	force	nor	signal
all	function	not	shared
and		null	sla
architecture	generate		sll
array	generic	of	sra
assert	group	on	srl
assume	guarded	open	strong
attribute		or	subtype
	if	others
begin	impure	out	then
block	in		to
body	inertial	package	transport
buffer	inout	parameter	type
bus	is	port
		postponed	unaffected
case	label	procedure	units
component	library	process	until
configuration	linkage	property	use
constant	literal	protected
context	loop	private	variable
cover		pure	view
	map		vpkg
default	mod	range	vmode
disconnect		record	vprop
downto		register	vunit
		reject
else		release	wait
elsif		rem	when
end		report	while
entity		restrict	with
exit		return
		rol	xnor
		ror	xor

1076-2008 - IEEE Standard VHDL Language Reference Manual, 15.10 Reserved words

abs	fairness	nand	select
access	file	new	sequence
after	for	next	severity
alias	force	nor	signal
all	function	not	shared
and		null	sla
architecture	generate		sll
array	generic	of	sra
assert	group	on	srl
assume	guarded	open	strong
assume_guarantee		or	subtype
attribute	if	others
	impure	out	then
begin	in		to
block	inertial	package	transport
body	inout	parameter	type
buffer	is	port
bus		postponed	unaffected
	label	procedure	units
case	library	process	until
component	linkage	property	use
configuration	literal	proteccted
constant	loop	pure	variable
context			vmode
cover	map	range	vprop
	mod	record	vunit
default		register
disconnect		reject	wait
downto		release	when
		rem	while
else		report	with
elsif		restrict
end		restrict_guarantee	xnor
entity		return	xor
exit		rol
		ror

1076-2002 - IEEE Standard VHDL Language Reference Manual, 13.9 Reserved words

abs	file	nand	select
access	for	new	severity
after	function	next	signal
alias		nor	shared
all	generate	not	sla
and	generic	null	sll
architecture	group		sra
array	guarded	of	srl
assert		on	subtype
attribute	if	open
	impure	or	then
begin	in	others	to
block	inertial	out	transport
body	inout		type
buffer	is	package
bus		port	unaffected
	label	postponed	units
case	library	procedural	until
component	linkage	procedure	use
configuration	literal	process
constant	loop	protected	variable
		pure
disconnect	map		wait
downto	mod	range	when
		record	while
else		reference	with
elsif		register
end		reject	xnor
entity		rem	xor
exit		report
		return
		rol
		ror

1076-1993 - IEEE Standard VHDL Language Reference Manual, 13.9 Reserved words

abs	file	nand	select
access	for	new	severity
after	function	next	signal
alias		nor	shared
all	generate	not	sla
and	generic	null	sll
architecture	group		sra
array	guarded	of	srl
assert		on	subtype
attribute	if	open
	impure	or	then
begin	in	others	to
block	inertial	out	transport
body	inout		type
buffer	is	package
bus		port	unaffected
	label	postponed	units
case	library	procedure	until
component	linkage	process	use
configuration	literal	pure
constant	loop		variable
		range
disconnect	map	record	wait
downto	mod	register	when
		reject	while
else		rem	with
elsif		report
end		return	xnor
entity		rol	xor
exit		ror

Parameters

No parameters.