FSM #2: state_reg

Summary

Graph	Name	Location	Reset State	States	Unreachable States	Deadlock States	Livelock States	Input Signals	Output Signals
	state_reg	cache.vhd#43	2’00	Count: 4 2’00 2’01 2’10 2’11	Count: 0	Count: 0	Count: 0	6	5

Input Signals

Count: 6

Name	Declaration
address_next	cache.vhd#26
byte_we_next	cache.vhd#27
cache_tag_out	cache.vhd#50
cache_tag_reg	cache.vhd#49
mem_busy	cache.vhd#29
state	cache.vhd#44

Output Signals

Count: 5

Name	Declaration
cache_checking	cache.vhd#32
cache_miss	cache.vhd#33
cache_tag_reg	cache.vhd#49
state	cache.vhd#44
state_next	cache.vhd#45

Transitions

Count: 18

From	To	Input Control Signals
2’00	2’00	address_next: cache.vhd#26
2’00	2’01	address_next: cache.vhd#26 byte_we_next: cache.vhd#27
2’00	2’11	address_next: cache.vhd#26 byte_we_next: cache.vhd#27
2’01	2’00	address_next: cache.vhd#26 state: cache.vhd#44
2’01	2’00	cache_tag_out: cache.vhd#50 cache_tag_reg: cache.vhd#49 state: cache.vhd#44
2’01	2’01	address_next: cache.vhd#26 byte_we_next: cache.vhd#27 state: cache.vhd#44
2’01	2’10	cache_tag_out: cache.vhd#50 cache_tag_reg: cache.vhd#49 state: cache.vhd#44
2’01	2’11	address_next: cache.vhd#26 byte_we_next: cache.vhd#27 state: cache.vhd#44
2’10	2’00	address_next: cache.vhd#26 state: cache.vhd#44
2’10	2’01	address_next: cache.vhd#26 byte_we_next: cache.vhd#27 state: cache.vhd#44
2’10	2’10	mem_busy: cache.vhd#29 state: cache.vhd#44
2’10	2’11	address_next: cache.vhd#26 byte_we_next: cache.vhd#27 state: cache.vhd#44
2’10	2’11	mem_busy: cache.vhd#29 state: cache.vhd#44
2’11	2’00	address_next: cache.vhd#26 state: cache.vhd#44
2’11	2’00	mem_busy: cache.vhd#29 state: cache.vhd#44
2’11	2’01	address_next: cache.vhd#26 byte_we_next: cache.vhd#27 state: cache.vhd#44
2’11	2’11	address_next: cache.vhd#26 byte_we_next: cache.vhd#27 state: cache.vhd#44
2’11	2’11	mem_busy: cache.vhd#29 state: cache.vhd#44