HDL1013: All clocks should be generated within a unique clock management module

Summary

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Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags
MEDIUM	-	HIGH	Adaptability | Modular	2h	synthesis, bug-finder, cnes, clock, cnes-std-04400, linty-ultra

Description

A dedicated clock management module brings a lot in terms of reuse and portability. Because all vendor-specific clocking elements such as PLLs, clock multiplexers and clock buffers are generated within the same module, it is easier to replace this module to target other FPGAs.

Parameters

No parameters.