060a32d5-35dc-423c-8c97-a36247137b82

Summary

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Rule	Message	Location	Effort	Reliability	Security	Maintainability
HDL1001	Review clock domain crossing between 'u2_ddr.cycle_count' (target) and 'u1_plama.u1_cpu.u2_mem_ctrl.address_reg' (origin)	ddr_ctrl.vhd#265	0min	HIGH	-	-