0f6aab44-08a5-479a-8f1c-23400002c3c5

Summary

Count: 1

RuleMessageLocationEffortReliabilitySecurityMaintainability
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#17420minHIGH--