Linty HDL Designer (HTML Report)
v1.2.3
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Clock Domains
Clock Domains
Clock Management Module (CMM)
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Linty HDL Designer (HTML Report)
v1.2.3
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VHDL316
Too many ports. Actual: 16. Allowed: 6. Split this entity into single-responsibility entities.
control.vhd#27
20min
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MEDIUM