4749edb4-e567-4e6c-abd7-85615b55e29c
Summary
| Rule | Message | Location | Effort | Reliability | Security | Maintainability |
|---|---|---|---|---|---|---|
| HDL1001 | Review clock domain crossing between 'u2_ddr.cycle_count' (target) and 'u1_plama.opt_cache2.u_cache.state_reg' (origin) | 0min | HIGH | - | - |