Linty HDL Designer (HTML Report)
v1.2.3
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Clock Domains
Clock Domains
Clock Management Module (CMM)
Reset Domains
Global Reset Domains
Local Reset Domains
Reset Management Module (RMM)
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VHDL
Verilog / SystemVerilog
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Linty HDL Designer (HTML Report)
v1.2.3
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VHDL315
Implement this empty conditional branch or remove it.
control.vhd#440
20min
HIGH
-
-