Linty HDL Designer (HTML Report)
v1.2.3
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Design Hierarchy
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Dependencies
VHDL Entities
VHDL Packages
Clock Domains
Clock Domains
Clock Management Module (CMM)
Reset Domains
Global Reset Domains
Local Reset Domains
Reset Management Module (RMM)
Clock Domain Crossings (CDC)
Reset Domain Crossings (RDC)
Unsynchronized Async Reset Release
Finite State Machines (FSM)
Combinational Loops
Latches
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VHDL
Verilog / SystemVerilog
HDL
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VHDL
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HDL
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HDL
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VHDL
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Linty HDL Designer (HTML Report)
v1.2.3
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HDL1002
Reduce the number of clock domains in this design. Maximum allowed number: 1. Actual number: 3.
plasma_3e.vhd#19
4h
HIGH
-
MEDIUM