Linty HDL Designer (HTML Report)
v1.2.3
Summary Report
Design Hierarchy
Summary
Dependencies
VHDL Entities
VHDL Packages
Clock Domains
Clock Domains
Clock Management Module (CMM)
Reset Domains
Global Reset Domains
Local Reset Domains
Reset Management Module (RMM)
Clock Domain Crossings (CDC)
Reset Domain Crossings (RDC)
Unsynchronized Async Reset Release
Finite State Machines (FSM)
Combinational Loops
Latches
Custom Graphs
Quality Profiles
VHDL
Verilog / SystemVerilog
HDL
Coding Quality
Measures
Opened Issues
VHDL
Verilog / SystemVerilog
HDL
Accepted Issues
VHDL
Verilog / SystemVerilog
HDL
False-Positive Issues
VHDL
Verilog / SystemVerilog
HDL
Linty HDL Designer (HTML Report)
v1.2.3
d9dfacc2-1cae-4f1c-8df4-601b39095993
View page source
d9dfacc2-1cae-4f1c-8df4-601b39095993
Summary
Count:
1
Clear filters
Rule
Message
Location
Effort
Reliability
Security
Maintainability
VHDL1061
Rename this clock signal to preserve its name across the design. Source signal name: CLK_50MHZ.
reg_bank.vhd#22
30min
MEDIUM
-
HIGH