VERILOG2014: An output port that is never given a value should be removed

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

MEDIUM	-	-	Intentionality \| Logical	10min	synthesis, vscode, linter, simulation, dead-code

module fly(
  input x,
  output y // Noncompliant: Output port 'y' is never given a value
);
endmodule

An output port that is never given a value should be removed.

No parameters.