VERILOG2037: Duplicated timing paths should be removed

Summary

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Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags
HIGH	-	-	Intentionality | Logical	10min	synthesis, vscode, simulation, linter

Description

More than one specify timing path was given for a particular pair of input and output terminals in a module.

Duplicated timing paths should be removed.

Noncompliant code example

module fly(input a, output b);
  specify
    (a => b) = 1;
    (a => b) = 2; // Noncompliant
  endspecify
endmodule

Compliant solution

module fly(input a, output b);
  specify
    (a => b) = 1;
  endspecify
endmodule

Parameters

No parameters.