VERILOG2044: Empty assignment pattern literals should not be used

Summary

Count: 1

Clear filters

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags
-	-	LOW	Intentionality | Clear	5min	synthesis, portability, vscode, linter, simulation

Description

Noncompliant code example

int foo[] = '{};

Even if it is supported by some tools, empty assignment pattern literals are not allowed by SystemVerilog standard. Refrain using such a syntax to keep your code portable.

Parameters

No parameters.