VERILOG2059: Formatting multi-bit nets with the “%v” specifier should be avoided

Summary

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Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags
LOW	-	-	Consistency | Conventional	5min	portability, synthesis, vscode, linter, simulation

Description

Formatting multi-bit nets with the %v specifier is not allowed in SystemVerilog.

Even if most tools allow it, refrain from using this syntax to keep your code portable.

Noncompliant code example

module fly;
  wire [3:0] w;
  initial $display("%v", w);
endmodule

Parameters

No parameters.