VERILOG2061: Implicit conversions between two unrelated types should be avoided

Summary

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Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags
HIGH	-	-	Intentionality | Logical	10min	synthesis, vscode, linter, simulation

Description

An implicit conversion in an expression converts between two unrelated types. SystemVerilog allows this for all packed integral types but it often indicates a mistake in the code.

Noncompliant code example

module fly;
  struct packed { logic a; int b; } foo;
  union packed { int a; int b; } bar;
  initial foo = bar;
endmodule

Parameters

No parameters.