VERILOG2072: Timing control edge expression should not be wider than one bit

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

HIGH	-	-	Intentionality \| Logical	10min	synthesis, vscode, simulation, linter

Description

Noncompliant code example

module fly;
  int i;
  always @(posedge i) begin end
endmodule

Compliant solution

module fly;
  logic i;
  always @(posedge i) begin end
endmodule

A timing control edge expression (posedge, negedge, etc.) is wider than one bit, which can indicate a mistake since only changes to the first bit will trigger the edge.

Parameters

No parameters.