VERILOG2096: An implicit conversion should not change the signedness of an integer type

Summary

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Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags
HIGH	-	-	Intentionality | Logical	5min	synthesis, vscode, simulation, linter

Description

An implicit conversion changes the signedness of an integer type (from signed to unsigned or vice versa), which can lead to unexpected behaviors.

Noncompliant code example

module fly;
  logic signed [31:0] a;
  logic [31:0] b;
  assign b = a;
endmodule

Compliant solution

module fly;
  logic signed [31:0] a;
  logic signed [31:0] b;
  assign b = a;
endmodule

Parameters

No parameters.