VERILOG2098: Parameters should not be used inside “specify” blocks

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

LOW	-	-	Consistency \| Conventional	10min	synthesis, portability, vscode, linter, simulation

module fly(input [1:0] a, output [1:0] b);
  parameter p = 1;
  specify
    (a[p] => b[0]) = 1;
  endspecify
endmodule

module fly(input [1:0] a, output [1:0] b);
  specify
    (a[1] => b[0]) = 1;
  endspecify
endmodule

The SystemVerilog standard disallows using parameters inside of specify blocks.

Even if most tools allow them, stick to the standard to keep your code portable.

No parameters.