VHDL1013: “rising_edge” and “falling_edge” functions should be used to detect clock transitions

Summary

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Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags
MEDIUM	-	-	Intentionality | Logical	10min	synthesis, bug-finder, clock, linty-ultra

Description

To improve reliability, use rising_edge and falling_edge functions instead of other clock transition implementations such as:

• clk'event and clk='1'
• not clk'stable and clk='1'

Articles & blog posts

• Difference between rising_edge(clk) and (clk'event and clk='1')

Noncompliant code example

process(clk) is
begin
  if clk'event and clk='1' then -- Noncompliant
    o1 <= not i1;
  end if;
end process;

Compliant solution

process(clk) is
begin
  if rising_edge(clk) then -- Compliant
    o1 <= not i1;
  end if;
end process;

Parameters

No parameters.