VHDL157: std_logic_vector signals should define a range
Summary
| Reliability | Security | Maintainability | Code attribute | Effort to fix | Tags |
|---|---|---|---|---|---|
| LOW | - | - | Intentionality | Logical | 5min | synthesis, vscode, simulation, linter |
Description
Noncompliant code example
signal sig : std_logic_vector; -- Noncompliant: Range not set
Compliant solution
signal sig : std_logic_vector(2 downto 0);
This rule raises an issue if an std_logic_vector does not define a range.
Parameters
No parameters.