VHDL229: Global signals should not be used in design

Summary

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Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags
HIGH	-	-	Intentionality | Logical	10min	synthesis, vscode, linter

Description

Noncompliant code example

package my_package is
  signal global_signal : std_logic := '0';
end;

Global signals cannot be used in design as they cannot be synthesized.

Parameters

No parameters.