VHDL305: “while” loops should not be used for synthesis

Summary

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Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags
-	-	MEDIUM	Intentionality | Logical	20min	synthesis, vscode, linter

Description

Some tools do not support while loops for synthesis. Thus, for better portability, use for loops instead.

Noncompliant code example

while i < 100 loop
  ...
end loop;

Compliant solution

for i in 0 to 100 loop
  ...
end loop;

Parameters

No parameters.