VHDL323: Only one generic should be declared or mapped per line

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

-	-	LOW	Intentionality \| Clear	5min	synthesis, vscode, linter, simulation

Declaring multiple items on a single line reduces readability.

This rule enforces that there is at most one generic declaration or mapping per line.

component my_component
  generic (
    a, b : in std_logic
  );
end component;

i1: comp generic map (
  a => '0', b => '0'
);

component my_component
  generic (
    a : in std_logic;
    b : in std_logic
  );
end component;

i1: comp generic map (
  a => '0',
  b => '0'
);

No parameters.