FSM #1: state_prev

Summary

Graph

Name

Location

Reset State

States

Unreachable States

Deadlock States

Livelock States

Input Signals

Output Signals

state_prev

ddr_ctrl.vhd#114

4’0000

Count: 9
4’0000
4’0001
4’0010
4’0011
4’0100
4’0101
4’0110
4’0111
4’1000

Count: 0

10

6

Input Signals

Count: 10

Name	Declaration
SD_BA	ddr_ctrl.vhd#76
active	ddr_ctrl.vhd#67
address	ddr_ctrl.vhd#63
bank_open	ddr_ctrl.vhd#124
byte_we	ddr_ctrl.vhd#64
ddr_proc.bank_index	ddr_ctrl.vhd#139
no_start	ddr_ctrl.vhd#68
no_stop	ddr_ctrl.vhd#69
refresh_cnt	ddr_ctrl.vhd#115
write_prev	ddr_ctrl.vhd#119

Output Signals

Count: 6

Name	Declaration
SD_CAS	ddr_ctrl.vhd#80
SD_RAS	ddr_ctrl.vhd#79
SD_WE	ddr_ctrl.vhd#81
ddr_proc.command	ddr_ctrl.vhd#138
ddr_proc.state_current	ddr_ctrl.vhd#140
pause	ddr_ctrl.vhd#70

Transitions

Count: 22

From	To	Input Control Signals
4’0000	4’0000	active: ddr_ctrl.vhd#67
4’0000	4’0000	active: ddr_ctrl.vhd#67 byte_we: ddr_ctrl.vhd#64
4’0000	4’0001	active: ddr_ctrl.vhd#67 byte_we: ddr_ctrl.vhd#64
4’0001	4’0001	active: ddr_ctrl.vhd#67 no_start: ddr_ctrl.vhd#68 refresh_cnt: ddr_ctrl.vhd#115
4’0001	4’0010	active: ddr_ctrl.vhd#67 no_start: ddr_ctrl.vhd#68 refresh_cnt: ddr_ctrl.vhd#115
4’0001	4’0111	refresh_cnt: ddr_ctrl.vhd#115
4’0010	4’0011
4’0011	4’0010	SD_BA: ddr_ctrl.vhd#76 active: ddr_ctrl.vhd#67 address: ddr_ctrl.vhd#63 bank_open: ddr_ctrl.vhd#124 ddr_proc.bank_index: ddr_ctrl.vhd#139 no_start: ddr_ctrl.vhd#68 refresh_cnt: ddr_ctrl.vhd#115
4’0011	4’0011	SD_BA: ddr_ctrl.vhd#76 active: ddr_ctrl.vhd#67 address: ddr_ctrl.vhd#63 bank_open: ddr_ctrl.vhd#124 byte_we: ddr_ctrl.vhd#64 ddr_proc.bank_index: ddr_ctrl.vhd#139 no_start: ddr_ctrl.vhd#68 refresh_cnt: ddr_ctrl.vhd#115
4’0011	4’0011	SD_BA: ddr_ctrl.vhd#76 active: ddr_ctrl.vhd#67 address: ddr_ctrl.vhd#63 bank_open: ddr_ctrl.vhd#124 byte_we: ddr_ctrl.vhd#64 ddr_proc.bank_index: ddr_ctrl.vhd#139 no_start: ddr_ctrl.vhd#68 refresh_cnt: ddr_ctrl.vhd#115 write_prev: ddr_ctrl.vhd#119
4’0011	4’0011	SD_BA: ddr_ctrl.vhd#76 active: ddr_ctrl.vhd#67 address: ddr_ctrl.vhd#63 bank_open: ddr_ctrl.vhd#124 ddr_proc.bank_index: ddr_ctrl.vhd#139 no_start: ddr_ctrl.vhd#68 refresh_cnt: ddr_ctrl.vhd#115 write_prev: ddr_ctrl.vhd#119
4’0011	4’0011	active: ddr_ctrl.vhd#67 no_start: ddr_ctrl.vhd#68 refresh_cnt: ddr_ctrl.vhd#115
4’0011	4’0011	refresh_cnt: ddr_ctrl.vhd#115 write_prev: ddr_ctrl.vhd#119
4’0011	4’0100	SD_BA: ddr_ctrl.vhd#76 active: ddr_ctrl.vhd#67 address: ddr_ctrl.vhd#63 bank_open: ddr_ctrl.vhd#124 byte_we: ddr_ctrl.vhd#64 ddr_proc.bank_index: ddr_ctrl.vhd#139 no_start: ddr_ctrl.vhd#68 refresh_cnt: ddr_ctrl.vhd#115 write_prev: ddr_ctrl.vhd#119
4’0011	4’0111	SD_BA: ddr_ctrl.vhd#76 active: ddr_ctrl.vhd#67 address: ddr_ctrl.vhd#63 bank_open: ddr_ctrl.vhd#124 ddr_proc.bank_index: ddr_ctrl.vhd#139 no_start: ddr_ctrl.vhd#68 refresh_cnt: ddr_ctrl.vhd#115 write_prev: ddr_ctrl.vhd#119
4’0011	4’0111	refresh_cnt: ddr_ctrl.vhd#115 write_prev: ddr_ctrl.vhd#119
4’0100	4’0101
4’0101	4’0110
4’0110	4’0011	no_stop: ddr_ctrl.vhd#69
4’0110	4’0110	no_stop: ddr_ctrl.vhd#69
4’0111	4’1000
4’1000	4’0001